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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50111-1E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
8M (x 16) FLASH MEMORY & 2M (x 16) STATIC RAM
MB84VD2008-10/MB84VD2009-10
s FEATURES
* Power supply voltage of 2.7 to 3.6 V * High performance 100 ns maximum access time * Operating Temperature -20 to +85C -- FLASH MEMORY * Simultaneous operations Read-while Erase or Read-while-Program * Minimum 100,000 write/erase cycles * Sector erase architecture Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VD2008: Top sector MB84VD2009: Bottom sector * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please refer to "MBM29DL800TA/BA" data sheet in detailed function -- SRAM * Power dissipation Operating : 50 mA max. Standby : 50 A max. * Data retention supply voltage: 2.0 V to 3.6 V
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VD2008-10/MB84VD2009-10
s BLOCK DIAGRAM
VCCf A0 to A18 A0 to A18 8 M bit Flash Memory VSS
RY/BY
RESET CEf
DQ0 to DQ15 VCCs A0 to A16 VSS
LBs UBs WE OE CEs
2 M bit Static RAM
2
MB84VD2008-10/MB84VD2009-10
s PIN ASSIGNMENTS
(Top View) A
6 5 4 3 2 1 CEs A10 OE A11 A13 WE
B
VSS DQ5 DQ7 A8 A17 VCCs
C
DQ1 DQ2 DQ4 A5 UBs A16
D
A1 A0 DQ0 DQ8 CEf VSS
E
A2 A3 A6 DQ3 DQ10 DQ9
F
A4 A7 A18 DQ12 VCCf DQ11
G
N.C. RY/BY RESET A12 DQ6 DQ13
H
A9 A14 A15 LBs DQ15 DQ14
Table 1 Pin Configuration
Pin A0 to A16 A17 to A18 DQ0 to DQ15 CEf CEs OE WE RY/BY UBs LBs RESET N.C. VSS VCCf VCCs
Function Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM)
Input/ Output I I I/O I I I I O I I I -- Power Power Power
3
MB84VD2008-10/MB84VD2009-10
s PRODUCT LINE UP
Flash Memory Ordering Part No. VCC = 3.0 V
+0.6 V -0.3 V
SRAM
MB84VD2008-10/MB84VD2009-10 100 100 40 85 85 45
Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
s BUS OPERATIONS
Table 2 User Bus Operations Operation (1), (3) Full Standby Output Disable Read from Flash (2) Write to Flash Read from SRAM CEf H H L L L H CEs H L H H H L OE X H X H L H L WE X H X H H L H LBs X X H X X X L H L L Write to SRAM Flash Hardware Reset H X L H X X L X H L X UBs X X H X X X L L H L L H X DQ0 to DQ7 DQ8 to DQ15 RESET HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DIN DOUT HIGH-Z DOUT DIN HIGH-Z DIN HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DIN DOUT DOUT HIGH-Z DIN DIN HIGH-Z HIGH-Z L H H H H H H
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes: 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CEs = VIL at a time.
4
MB84VD2008-10/MB84VD2009-10
s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
* Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes. * Individual-sector, multiple-sector, or bulk-erase capability.
(x8) 16K byte/8K word
(x16) 64K byte/32K word
(x8)
(x16)
FFFFFH 7FFFFH FC000H 7E000H 32K byte/16K word F4000H 7A000H 8K byte/4K word F2000H 79000H 8K byte/4K word Bank 1 8K byte/4K word EE000H 77000H 8K byte/4K word EC000H 76000H 32K byte/16K word E4000H 72000H Bank 2 16K byte/8K word E0000H 70000H 64K byte/32K word D0000H 68000H 64K byte/32K word C0000H 60000H 64K byte/32K word B0000H 58000H 64K byte/32K word A0000H 50000H 64K byte/32K word 90000H 48000H 64K byte/32K word 80000H 40000H 64K byte/32K word Bank 2 64K byte/32K word 60000H 30000H 64K byte/32K word 50000H 28000H 64K byte/32K word 40000H 20000H Bank 1 64K byte/32K word 30000H 18000H 64K byte/32K word 20000H 10000H 64K byte/32K word 10000H 08000H 64K byte/32K word 00000H 00000H MBM29DL800TA Sector Architecture MB84VD2008 Sector Architecture 16K byte/8K word 32K byte/16K word 8K byte/4K word 8K byte/4K word 8K byte/4K word 8K byte/4K word 70000H 38000H 32K byte/16K word 16K byte/8K word 64K byte/32K word 64K byte/32K word 64K byte/32K word 64K byte/32K word 64K byte/32K word 64K byte/32K word 64K byte/32K word 64K byte/32K word 64K byte/32K word F0000H 78000H 64K byte/32K word 64K byte/32K word 64K byte/32K word 64K byte/32K word
FFFFFH 7FFFFH F0000H 78000H E0000H 70000H D0000H 68000H C0000H 60000H B0000H 58000H A0000H 50000H 90000H 48000H 80000H 40000H 70000H 38000H 60000H 30000H 50000H 28000H 40000H 20000H 30000H 18000H 20000H 10000H 1C000H 0C000H 14000H 0A000H 12000H 09000H 10000H 08000H 0E000H 07000H 0C000H 06000H 04000H 02000H 00000H 00000H MBM29DL800BA Sector Architecture MB84VD2009 Sector Architecture
5
MB84VD2008-10/MB84VD2009-10
Table 4 Sector Address Tables (MB84DV2008)
Sector Address Bank Sector Bank Address A18 A17 A16 A15 A14 A13 A12 SA0 SA1 SA2 SA3 SA4 SA5 SA6 Bank 2 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank 1 SA18 SA19 SA20 SA21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 X X 16/8 0 0 0 0 0 1 0 1 X 32/16 8/4 8/4 78000H to 78FFFH 79000H to 79FFFH 7A000H to 7BFFFH, 7C000H to 7DFFFH 7E000H to 7FFFFH 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 X 0 1 8/4 8/4 X X X X X X X 0 0 X X X X X X X 0 1 X X X X X X X X X 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16/8 38000H to 3FFFFH 40000H to 47FFFH 48000H to 4FFFFH 50000H to 57FFFH 58000H to 5FFFFH 60000H to 67FFFH 68000H to 6FFFFH 70000H to 71FFFH 72000H to 73FFFH, 74000H to 75FFFH 76000H to 76FFFH 77000H to 77FFFH 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 00000H to 07FFFH 08000H to 0FFFFH 10000H to 17FFFH 18000H to 1FFFFH 20000H to 27FFFH 28000H to 2FFFFH 30000H to 37FFFH Sector Size (Kbytes/ Kwords) (x16) Address Range
6
MB84VD2008-10/MB84VD2009-10
Table 5 Sector Address Tables (MB84DV2009) Sector Address Bank Sector Bank Address A18 SA21 SA20 SA19 SA18 SA17 SA16 SA15 Bank 2 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 Bank 1 SA3 SA2 SA1 SA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 X X 16/8 1 1 1 1 1 0 1 0 X 32/16 8/4 8/4 07000H to 07FFFH 06000H to 06FFFH 04000H to 05FFFH, 02000H to 03FFFH 00000H to 01FFFH 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 X 1 0 8/4 8/4 X X X X X X X 1 1 X X X X X X X 1 0 X X X X X X X X X 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16/8 40000H to 47FFFH 38000H to 3FFFFH 30000H to 37FFFH 28000H to 2FFFFH 20000H to 27FFFH 18000H to 1FFFFH 10000H to 17FFFH 0E000H to 0FFFFH 0A000H to 0BFFFH, 0C000H to 0DFFFH 09000H to 09FFFH 08000H to 08FFFH 1 1 1 1 1 1 1 A17 1 1 1 1 0 0 0 A16 1 1 0 0 1 1 0 A15 1 0 1 0 1 0 1 A14 X X X X X X X A13 X X X X X X X A12 X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 78000H to 7FFFFH 70000H to 77FFFH 68000H to 6FFFFH 60000H to 67FFFH 58000H to 5FFFFH 50000H to 57FFFH 48000H to 4FFFFH Sector Size (Kbytes/ Kwords) (x16) Address Range
7
MB84VD2008-10/MB84VD2009-10
Table 6. 1 Flash Memory Autoselect Codes Type Manufacturer's Code MB84VD2008 Device Code MB84VD2009 VIL VIL VIH 22CBH A6 VIL VIL A1 VIL VIL A0 VIL VIH Code (HEX) 04H 224AH
Table 6. 2 Expanded Autoselect Code Table Type Manufacturer's Code Device Code MB84VD2008 MB84VD2009
Code 0004H 224AH 22CBH DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1
8
MB84VD2008-10/MB84VD2009-10
Table 7 Command Sequence
Read/Reset Read/Reset Autoselect Program Chip Erase Sector Erase Bus Write Cycles Req'd
Flash Memory Command Definitions Fifth Bus Sixth Bus Write Cycle Write Cycle Addr. Data Addr. Data -- -- -- -- -- -- -- -- -- -- -- -- 555H SA -- -- -- -- -- -- -- -- 10H 30H -- -- -- -- -- --
1 3 3 4 6 6 1 1 3 2 2 4
First Bus Second Bus Third Bus Fourth Bus Write Cycle Write Cycle Write Cycle Read/Write Cycle Addr. Data Addr. Data Addr. Data Addr. Data XXXH F0H -- -- -- -- -- -- 555H AAH 2AAH 55H 555H F0H RA RD (BA) 555H AAH 2AAH 55H 90H -- -- 555H 555H AAH 2AAH 55H 555H A0H PA PD 555H AAH 2AAH 55H 555H 80H 555H AAH 555H AAH 2AAH 55H 555H 80H 555H AAH BA BA B0H 30H -- -- -- -- -- -- 555H -- -- SPA -- -- 20H -- -- 40H -- -- -- -- -- SPA -- -- -- -- -- SD
-- -- 2AAH 55H 2AAH 55H -- -- -- -- -- -- -- -- -- -- -- --
Erase Suspend Erase Resume
Set to Fast Mode Fast Program * Reset from Fast Mode * Extended Sector Protect
555H AAH 2AAH 55H XXXH A0H BA PA PD
90H XXXH F0H SPA 60H
XXXH 60H
Notes: 1. Address bits A11 to A18 = X = "H" or "L" for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA). 2. Bus operations are defined in Tables 2 and 3. 3. RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A16 to A18) 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse. 5. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. * : This command is valid while Fast Mode.
9
MB84VD2008-10/MB84VD2009-10
s ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. -55C to +125C Ambient Temperature with Power Applied .................................................................. -25C to +85C Voltage with Respect to Ground All pins (Note) .......................................................... -0.3 V to VCCf +0.5 V -0.3 V to VCCs +0.5 V VCCf/VCCs Supply (Note) .............................................................................................. -0.3 V to +4.6 V Note: Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitions, inputs may negativeovershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf +0.5 V or VCCs +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING RANGES
Commercial Devices Ambient Temperature (TA) .........................................................................-20C to +85C VCCf/VCCs Supply Voltages.........................................................................+2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
10
MB84VD2008-10/MB84VD2009-10
s DC CHARACTERISTICS
Parameter Symbol
Parameter Description Input Leakage Current Output Leakage Current
Test Conditions -- --
Min. -1.0 -1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 1.5 -- 1 -- -- -- -- -- -- --
Max. +1.0 +1.0 20 10 35 45 45 35 60 12 50 6 5 5 2 2.5 55 3 60 2 5 50 0.6
Unit A A mA mA mA mA mA mA mA mA mA A A mA A A A A
ILI ILO ICC1f
Flash VCC Active Current VCCf = VCC Max., CEf = VIL tCYCLE = 10 MHz OE = VIH (Read) tCYCLE = 5 MHz Flash VCC Active Current VCCf = VCC Max., CEf = VIL, OE = VIH ICC2f (Program/Erase) Flash VCC Active Current ICC3f** CE = VIL, OE = VIH (Read-While-Program) Flash VCC Active Current ICC4f** CE = VIL, OE = VIH (Read-While-Erase) Flash VCC Active Current ICC5f (Erase-SuspendCE = VIL, OE = VIH Program) tCYCLE = min VCCs = VCC Max., SRAM VCC Active ICC1s Current CEs = VIL tCYCLE = 1 MHz tCYCLE = min CEs = 0.2 V, ICC2s SRAM VCC Active Current WE = VCCs - 0.2 V tCYCLE = 1 MHz Flash VCC Standby VCCf = VCC Max., CEf = VCCf 0.3 V ISB1f Current RESET = VCCf 0.3 V Flash VCC Standby ISB2f VCCf = VCC Max., RESET = VSS 0.3 V Current (RESET) ISB1s SRAM VCC Standby CEs = VIH Current VCCs = TA = 25C 3.0 V 10% TA = -20 to +85C ISB2s SRAM VCC Standby Current
VIL VIH VOL VOH VLKO
Input Low Level Input High Level Output Low Voltage Level Output High Voltage Level Flash Low VCC Lock-Out Voltage
VCCs = TA = 25C -- CEs = VCC -0.2 V 3.3 V TA = -20 to +85C -- 0.3 V -- TA = 25C VCCs = TA = -20 to +40C -- 3.0 V TA = -20 to +85C -- -- -0.3 -- 2.2 IOL = 2.1 mA, -- VCCf = VCCs = VCC Min. IOH = -500 A, VCC - 0.5 VCCf = VCCs = VCC Min. -- 2.3
A A A V VCC+0.3* V 0.4 -- 2.5 V V V
* : VCC indicate lower of VCCf or VCCs ** :Embedded Algorithm (program or erase) is in progress. (@5 MHz)
11
MB84VD2008-10/MB84VD2009-10
s AC CHARACTERISTICS
* CE Timing Parameter Symbols JEDEC -- Standard tCCR CE Recover Time -- Min. 0 ns
Description
Test Setup
-10
Unit
* Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CEs
* Read Only Operations Characteristics (Flash) Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- -- Standard tRC tACC tCEf tOE tDF tDF tOH tREADY tELFL tELFH Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode CE or BYTE Switching Low or High -- CEf = VIL OE = VIL OE = VIL -- -- -- -- -- -- Test Setup -10 (Note) Min. 100 -- -- -- -- -- 0 -- -- Max. -- 100 100 40 30 30 -- 20 5 ns ns ns ns ns ns ns s ns
Description
Unit
Note: Test Conditions-Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V 12
MB84VD2008-10/MB84VD2009-10
* Read Cycle (Flash)
tRC
Addresses Stable
ADDRESSES tACC
CEf
tOE tDF
OE
tOEH
WE
tCE
DQ
HIGH-Z
Output Valid
HIGH-Z
tRC ADDRESSES tACC tRH
Addresses Stable
RESET
tOH
DQ
HIGH-Z
Output Valid
13
MB84VD2008-10/MB84VD2009-10
* Erase/Program Operations (Flash) Parameter Symbols JEDEC tAVAV tAVWL tAVEL -- tWLAX tELAX -- tDVWH tWHDX -- -- -- tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- -- -- Standard tWC tAS tAS tASO tAH tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tVIDR tRB tRP tRH tEOE tBUSY tFLQZ tFHQV Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time (CEf to Addr.) Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time (CEf to Addr.) Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling -10 Min. 100 0 0 15 50 50 0 50 0 0 10 20 20 0 0 0 0 0 0 50 50 30 30 -- -- -- 50 4 500 0 500 200 -- -- -- 30 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 1 -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 -- -- -- -- -- -- 100 90 30 --
Description
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s sec sec s s ns ns ns ns ns ns ns ns
CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Byte Programming Operation Sector Erase Operation (Note 1) VCCf Setup Time Voltage Transition Time (Note 2) Rise Time to VID (Note 2) Recover Time from RY/BY RESET Pulse Width RESET Hold Time Before Read Delay Time from Embedded Output Enable Program/Erase Valid to RY/BY Delay BYTE Switching Low to Output High-Z BYTE Switching High to Output Active
Note : 1. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation. 14
MB84VD2008-10/MB84VD2009-10
* Write Cycle (WE control) (Flash)
3rd Bus Cycle
ADDRESSES 555H tWC tAS PA tAH
Data Polling
PA tRC
CEf
tCS tCH tCO
OE
tGHWL tWP tWPH tWHWH1 tFOE
WE
tDS tDH tOH
DQ
A0H
PD
DQ7
DOUT
DOUT
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence These waveforms are for the x16 mode. The addresses differ from x8 mode.
15
MB84VD2008-10/MB84VD2009-10
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle ADDRESSES 555H tWC tAS PA tAH
Data Polling PA
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH
DQ
A0H
PD
DQ7
DOUT
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence These waveforms are for the x16 mode. The addresses differ from x8 mode.
16
MB84VD2008-10/MB84VD2009-10
* AC Waveforms Chip/Sector Erase Operations (Flash)
ADDRESSES
555H tWC
2AAH tAS tAH
555H
555H
2AAH
SA*1
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS tDH AAH 55H 80H AAH 55H 30H for Sector Erase 10H/ 30H
DQ
tVCS
VCC
Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase. 2. These waveforms are for the x16 mode. The addresses differ from x8 mode.
17
MB84VD2008-10/MB84VD2009-10
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
* DQ7
Data DQ7 DQ7 = Valid Data High-Z
t WHWH1 or 2
DQ0 to DQ6
Data t BUSY
DQ0 to DQ6 = Output Flag t EOE
DQ0 to DQ6 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation). * AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO tAHT tAS
CE
tCEPH
WE
tOEH
tOEPH tOEH
OE
tDH tOE tCE *
DQ 6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
Stop
Toggling
Output Valid
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
18
MB84VD2008-10/MB84VD2009-10
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
* RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
* Timing Diagram for Word Mode Configuration (Flash)
CE
BYTE
Data Output (DQ0 to DQ7) tELFH tFHQV A-1 DQ15 Data Output (DQ0 to DQ14)
DQ0 to DQ14
DQ15/A-1
19
MB84VD2008-10/MB84VD2009-10
* Timing Diagram for Byte Mode Configuration (Flash)
CE
BYTE
tELFL
DQ0 to DQ14
Data Output (DQ0 to DQ14)
Data Output (DQ0 to DQ7)
DQ15/A-1
DQ15 tFLQZ
A-1
* BYTE Timing Diagram for Write Operations (Flash)
The falling edge of the last WE signal
CE or WE
BYTE
tSET (tAS)
Input Valid
tHOLD (tAH)
* Temporary Sector Unprotection (Flash)
VCC tVCS VID 3V RESET CE
tVIDR tVLHT
3V
WE
tVLHT RY/BY
Program or Erase Command Sequence
tVLHT
Unprotection period
20
MB84VD2008-10/MB84VD2009-10
* Back-to-back Read/Write Timing Diagram
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
Address
BA1
tAS
BA2 (555H)
tAH tACC
BA1
BA2 (PA)
BA1
tAS tAHT
BA2 (PA)
tCE
CE
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF
DQ
Valid Output
Valid Intput (A0H)
Valid Output
Valid Intput (PD)
Valid Output
Status
21
MB84VD2008-10/MB84VD2009-10
* Extended Sector Protection (Flash)
VCC tVCS
RESET tVIDR
tVLHT
Add
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE TIME-OUT
WE
Data
60H
60H
40H tOE
01H
60H
SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 s (min)
22
MB84VD2008-10/MB84VD2009-10
* Read Cycle (SRAM) Parameter Symbol tRC tAA tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Parameter Description Read Cycle Time Address Access Time Chip Enable (CEs) Access Time Output Enable Access Time UB, LB Access Time Chip Enable Low to Output Active Output Enable Low to Output Active UB, LB Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z UB, LB High to Output High-Z Output Data Hold Time Min. 85 -- -- -- -- 5 0 0 -- -- -- 10 Max. -- 85 85 45 45 -- -- -- 35 35 35 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
* Read Cycle (Note 1) (SRAM)
tRC ADDRESSES tAA tCO CEs tOD tOE OE tOH
tBA UB, LB tBE tOEE DOUT tCOE tBD
tODO
VALID DATA OUT
Note: 1. WE remains HIGH for the read cycle. 23
MB84VD2008-10/MB84VD2009-10
* Write Cycle (SRAM) Parameter Description Write Cycle Time Write Pulse Width Chip Enable to End of Write UB, LB Valid to End of Write Address Setup Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Min. 85 60 75 55 0 0 -- 0 35 0 Max. -- -- -- -- -- -- 35 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns Parameter Symbol tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH
* Write Cycle (Note 4) (WE control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CEs
tBW UB, LB tODW tOEW
DOUT
Note 2 tDS tDH
Note 3
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CEs goes LOW coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CEs goes HIGH coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
24
MB84VD2008-10/MB84VD2009-10
* Write Cycle (Note 4) (CEs control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CES
tBW UB, LB tBE tCOE DOUT tDS tDH tODW
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CEs goes LOW coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CEs goes HIGH coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
25
MB84VD2008-10/MB84VD2009-10
* Write Cycle (Note 4) (UB, LB Control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CEs
tBW UB, LB
tCOE DOUT tBE
tODW
tDS
tDH
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CEs goes LOW coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CEs goes HIGH coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
26
MB84VD2008-10/MB84VD2009-10
s ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limits Parameter Min. Sector Erase Time Byte Programming Time Word Programming Time Chip Programming Time Erase/Program Cycle -- -- -- -- 100,000 Typ. 1 8 16 8.4 -- Max. 10 300 360 TBD -- sec s s sec cycles Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Unit Comment
s DATA RETENTION CHARACTERISTICS (SRAM)
Parameter Symbol VDH IDDS2 tCDR tR Parameter Description Data Retention Supply Voltage Standby Current Chip Deselect to Data Retention Mode Time Recovery Time VDH = 3.0 V Min. 2.0 -- 0 5 Typ. -- -- -- -- Max. 3.6 50* -- -- Unit V A ns ms
* : 5 A (Max.) at TA = -20C to +40C * CE1s Controlled Data Retention Mode
VCCs
DATA RETENTION MODE
2.7 V
See Note 1 VIH VCCS -0.2 V tCDR
See Note 1
CEs
tR
GND
Notes:1.)When CEs is operating at the VIH min. level (2.2 V), the standby current is given by ISB1s during the transition of VCCs from 3.6 to 2.2 V. 27
MB84VD2008-10/MB84VD2009-10
s PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. TBD TBD TBD Max. TBD TBD TBD Unit pF pF pF
Note: Test conditions TA = 25C, f = 1.0 MHz
s HANDRING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
s CAUTION
1.)The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2.)For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector useing "Extended sector protect" command.
28
MB84VD2008-10/MB84VD2009-10
s PACKAGE
48-pin Plastic BGA
(BGA-48P-M06)
s PACKAGE DIMENSIONS
48-pin Plastic BGA (BGA-48P-M06) Note: The actual shape of coners may differ from the dimension.
11.000.15(.433.006)
1.400.20 (.055.008) 0.300.10 (.012.004)
7.000.15(.276.006)
10.000.15 (.394.006)
O0.400.10 (O.016.004)
5.000.15 (.197.006)
0.15(.006) 1st PIN
INDEX
1.000.15 (.039.006)
INDEX
C
1998 FUJITSU LIMITED MCM-M001-2-3
Dimension in mm (inches).
29
MB84VD2008-10/MB84VD2009-10
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9806 (c) FUJITSU LIMITED Printed in Japan
30

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